1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having spare memory cells for repairing a defective bit. More specifically, this invention relates to a semiconductor memory device capable of accurately detecting a program failure in a program of a defective address.
2. Description of the Background Art
FIG. 24 is a schematic diagram showing a configuration of a main part of a conventional semiconductor memory device. In FIG. 24, the semiconductor memory device includes a normal array 900 having a plurality of normal memory cells arranged in rows and columns; a spare array 902 having spare memory cells for repairing a defective memory cell in normal array 900; a normal row selection circuit 904 for selecting a memory cell row in normal array 900 in accordance with an internal address signal intAD; a spare address program circuit 906 for storing a defective address of normal array 900, and for generating, when the defective address is designated by internal address signal intAD, a spare row enable signal SRE and designating a spare memory cell row of spare array 902; and a spare row selection circuit 908 for driving a corresponding spare memory cell row of spare array 902 to a selected state in accordance with the output signal of defective address program circuit 906.
When defective address program circuit 906 have defective addresses designating spare memory cells in a plurality of rows in spare array 902 programmed therein, signals indicating whether or not internal address signal intAD designates the defective addresses are generated for the respective programmed defective addresses, and the spare row enable signal SRE is generated from the OR operation of these signals. Spare word lines are arranged corresponding to the respective defective addresses.
When spare row enable signal SRE is activated, the row selecting operations by normal row selection circuit 904 is inhibited. When the address of a defective memory cell row is designated in normal array 900, a spare memory cell row in spare array 902 is driven to the selected state. The defective normal memory cell row is replaced by the spare memory cell row, and the defective memory cell row is repaired equivalently. Defective memory cell row is repaired to improve the product yield.
In spare array 902, besides a spare row for repairing a defective memory cell row, there is provided a spare column for repairing a defective memory cell column in normal array 900 through replacement.
FIG. 25 shows the configuration of a defective address program circuit disclosed, for example, in Japanese Patent Laying-Open No. 11-203888. In defective address program circuit 906 shown in FIG. 25, whether a defective address is designated or not is determined in accordance with row address bits RA0 to RAn and complementary row address bits /RA0 to /RAn.
In FIG. 25 defective address program circuit 906 includes N-channel MOS transistors TR0 to TRn receiving row address bits RA0 to RAn at their gates, respectively; N-channel MOS transistors ZTR0 to ZTRn receiving complementary row address bits /RA0 to /RAn at their gates, respectively; fuse elements FU0 to FUn connected between the respective MOS transistors TR0 to TRn and a determination node 912; fuse elements ZFU0 to ZFUn connected between the respective MOS transistors ZTR0 to ZTRn and determination node 912; and a P-channel MOS transistor 910 for precharging determination node 912 to a power supply voltage Vcc level in accordance with a precharge instruction signal ZPR. The spare row enable signal SREi is generated at determination node 912. Each source of MOS transistors TR0 to TRn and ZTR0 to ZTRn is connected to a ground node.
In defective address program circuit 906 shown in FIG. 25, the fuse element corresponding to the bit attaining H level when a defective address is designated is blown by an energy ray such as a laser beam. For example, when an address (RA0 . . . RAn)=(100 . . . 01) is defective, fuse elements FU0 and FUn and ZFU1 to ZFUnxe2x88x921 are blown.
When there is no defective address, all the fuse elements are kept in the non-blown state.
The defective address program circuit is arranged for each spare row, and when spare row enable signal SREi is activated upon selecting a row, the corresponding spare row (word line) is driven to the selected state. To normal row selection circuit 904, the spare enable signal is generated in accordance with the OR operation of output signals SREi of the defective address program circuits provided for the respective spare rows.
In a precharge cycle, address bits RA0 to RAn and /RA0 to /RAn are all set at L level, and determination node 912 has a discharging path cut off and is precharged to a power supply voltage Vcc level by MOS transistor 910.
When a defective row address is designated in a row selecting operation, determination node 912 has no discharging path because the fuse element corresponding to the H level address bit is blown. Consequently, spare row enable signal SREi remains at H level, and spare row selection circuit 908 is activated to select the corresponding spare memory cell row in spare array 902.
Spare row enable signal SRE applied to normal row selection circuit 904 is activated in accordance with spare row enable signal SREi when a defective address is designated.
When an address other than the defective address is designated, the address bit, applied to the gate of the MOS transistor provided for a fuse element in the non-blown state out of fuse elements FU0 to FUn and ZFU0 to ZFUn, attains H level. Therefore, determination node 912 is discharged to the ground voltage level, and spare row enable signal SREi is driven to L level, and normal row selection circuit 904 selects a normal memory cell row in accordance with an internal address signal intAD. Spare row enable signal SREi is in the inactive state, and spare row selection circuit 908 remains in the inactive state.
The precharge instruction signal ZPR is activated in the stand-by cycle, and determination node 912 is precharged to the power supply voltage Vcc level. In the active cycle for selecting a memory cell, precharge instruction signal ZPR is at H level, and MOS transistor 910 remains non-conductive.
When programming a defective address, if the fuse elements are correctly blown, spare row enable signal SRE (SREi) attains either the power supply voltage Vcc level or the ground voltage level, depending on whether a defective address is designated or not. Thus, a defective memory cell is reliably replaced by a spare memory cell, to repair the defect.
When the blowing of fuse elements FU (FU0 to FUn) or ZFU (ZFU0 to ZFUn) is made unsuccessfully, even if a defective address is designated, spare row enable signal SRE (SREi) attains L level, and a spare memory cell is not selected. As a result, the defective row is not replaced by spare memory cells, and failure repairing is not made. In this case, the program failure of a defective address can be detected by testing the products before shipment.
However, when the blowing of the fuse elements is done incompletely, a small amount of current flows via the incompletely blown fuse element.
FIG. 26 is a diagram showing an example of a fuse element in an incompletely blown state. In FIG. 26, a fuse element FUi is incompletely blown and still partly connected. Under this condition, when an H level address bit is applied to the corresponding MOS transistor TRi, a minute current I flows from determination node 912 to the ground node.
When the defective address is designated, minute current I falls spare row enable signal SRE (SREi) to an intermediate voltage level, and there is caused the following two cases, depending on the voltage level of the spare row enable signal; spare row selection circuit 908 is activated to perform a spare row selecting operation, and normal row selection circuit 904 is activated to perform a normal row selecting operation. Since a defective memory cell is repaired in some cases and not repaired in the other cases, an intermittent defect occurs in the operation. This intermittent defect occurs in a defective address, so that it can also be detected through a test using various test patterns.
When spare row enable signal SRE is at an intermediate voltage level, both spare row selection circuit 908 and normal row selection circuit 904 might be put in the activated state depending on this voltage level, thereby causing a multi-selection (multiple selection of word lines) in which a defective normal word line and a spare word line are both driven to the selected state.
FIG. 27 is a schematic diagram showing the arrangement of memory cells on a normal word line NWL and a spare word line SPWL. In FIG. 27, bit lines BL0, /BL0 to BLm, /BLm are arranged in the direction crossing normal word line NWL and spare word line SPWL. These bit lines BL0, /BL0 to BLm, /BLm are disposed in pairs. Normal memory cells NMC are arranged corresponding to crossings of normal word line NWL and bit lines BL0, /BL1, . . . , /BLm. Spare memory cells SMC are arranged corresponding to crossings of spare word line SPWL and bit lines BL0, /BL1, . . . , /BLm.
In general, memory cells MC are arranged in a matrix of rows and columns in a memory cell array, the memory cells MC connected to the normal word line are used as normal memory cells NMC, and the memory cells connected to spare word line SPWL are used as spare memory cells SMC. In such a memory array, spare memory cells SMC and normal memory cells NMC are arranged forming a successive pattern.
Now, the case is considered where a defective normal word line NWL and spare word line SPWL are selected at the same time under the condition that defective normal word line NWL is the same in arrangement of associated memory cells as spare word line SPWL. In this case, the data stored in normal memory cells NMC and spare memory cells SMC are read out on the same bit lines. Furthermore, when a multi-selection occurs, data of the same logical level are written into and read out of spare memory cells SMC and normal memory cells NMC, making it impossible to identify the occurrence of a multi-selection.
In order to identify the presence or absence of a multi-selection, it is required to write data of different logical levels to a normal memory cell NMC and a spare memory cell SMC. In this case, it is necessary that after a defective address is programmed, a defective normal word line NWL is forcibly put into the selected state for writing a certain data pattern and a spare word line is forcibly driven into a selected state for writing a data pattern of logical levels opposite to the certain data pattern written to defective normal word line NWL.
In the case where a defective word line and the corresponding spare word line have different patterns of connected memory cells from each other, the memory cells on one word line are connected to bit line BL and the memory cells on the other word line are connected to complementary bit line /BL. Therefore, when a multi-selection occurs, the normal and the spare memory cells store data of opposite logical levels, and data read out has the same logical level as written data, which makes it impossible to detect a multi-selection.
Thus, when testing is performed by writing various data patterns, a defective address must be stored and a data pattern of logical levels inverse to the data pattern written to the defective address has to be written to spare word line SPWL only for detection of a multi-selection. In other words, data patterns of opposite logical levels are required to be written to a spare word line and the corresponding defective normal word line. When detection of a multi-selection is performed at the same time as the test for detecting the presence of memory cell leakage by storing various data patterns in memory cells, there arises a problem that the data patterns are restricted, and test data patterns are limited.
An object of the present invention is to provide a semiconductor memory device capable of reliably detecting whether a defective address program is being accurately performed.
Another object of the present invention is to provide a semiconductor memory device capable of accurately detecting whether a multi-selection of word lines occurs.
A semiconductor memory device according to the present invention includes: a plurality of normal memory cells arranged in rows and columns; a plurality of normal word lines arranged corresponding to the respective normal memory cell rows and connecting normal memory cells in the corresponding rows; a plurality of spare memory cells arranged in rows and columns with the columns shared with the normal memory cells; a plurality of spare word lines arranged corresponding to the respective spare memory cell rows and connecting spare memory cells in the corresponding rows; and a defective address program circuit for programming the address of a defective normal word line. This defective address program circuit includes a circuit for generating a coincidence indicating signal indicating the determination result of coincidence/non-coincidence between an external address and a programmed defective address.
The semiconductor memory device according to the present invention further includes: a word line selection circuit for selecting a corresponding word line from the plurality of normal word lines and a spare word line in accordance with the external address and the coincidence indicating signal; and an address conversion circuit for changing the correspondence relation between the external address and the plurality of spare word lines.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.